Synchronous digital circuits employ periodically oscillating signals, i.e., clock signals for coordinating various functions performed by the synchronous digital circuits. Synchronous digital circuits also employ the clock signals for sampling data. The clock signals are typically generated by a clock generating circuit, such as a ring current controlled oscillator, an inductor-capacitor voltage controlled oscillator (VCO), and the like. The clock signals that are employed by the synchronous digital circuits have oscillating frequencies ranging from a few Giga Hertz (GHz) to a few kilo Hertz (kHz).
To generate the clock signals at various frequencies, synchronous digital circuits typically employ a phase locked loop (PLL) for generating the clock signals. The PLL includes a clock generator circuit, a phase-frequency detector (PFD), a loop filter, a VCO, and a frequency divider circuit. The clock generating circuit generates a reference clock signal that has a reference oscillating frequency. The clock generating circuit is further connected to the PFD, and outputs the reference clock signal thereto. The PFD determines a phase difference between the reference clock signal and a division clock signal. Based on the phase difference between the reference clock signal and the division clock signal, the PFD generates a reference current, and outputs the reference current to the loop filter. The loop filter integrates the reference current, and generates a controlling voltage. The VCO receives the controlling voltage and generates a VCO clock signal that has a VCO oscillating frequency. The frequency divider circuit is connected between the VCO and the PFD. The frequency divider divides the VCO oscillating frequency by a division factor, and generates the division clock signal. Hence, the PLL controls the VCO oscillating frequency based on the division clock signal.
The frequency divider can be implemented as a multi-modulus frequency divider circuit. Prior multi-modulus frequency divider circuits have a high delay along their critical paths, which run on the highest frequency clock for the circuits. A higher delay can cause the frequency divider to generate the output clock signal erroneously due to a smaller margin for error in the critical stage timing, which leads to erroneous sampling of the data in synchronous digital circuits.